• DocumentCode
    1467402
  • Title

    Phase/frequency detectors for high-speed PLL applications

  • Author

    Woo-Young Choi

  • Volume
    34
  • Issue
    22
  • fYear
    1998
  • fDate
    10/29/1998 12:00:00 AM
  • Firstpage
    2120
  • Lastpage
    2121
  • Abstract
    Two new phase/frequency detectors (PFDs) are proposed that can overcome the speed and jitter limitations of conventional PFD schemes. One of the proposed circuits has a reset time of 0.32 ns and the other a reset time of 0.03 ns during the phase-locked loop capture process, according to HSPICE simulation with 0.8 μm CMOS process parameters
  • Keywords
    CMOS digital integrated circuits; digital phase locked loops; jitter; phase detectors; phase locked loops; 0.03 ns; 0.32 ns; 0.8 micron; CMOS IC; HSPICE simulation; high-speed PLL applications; jitter limitations; phase-locked loop; phase/frequency detectors; reset time;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19981493
  • Filename
    741321
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1467402