Title :
A 23-ps/2.1-mW ECL gate with an AC-coupled active pull-down emitter-follower stage
Author :
Toh, Kai-yap ; Chuang, Ching-Te ; Chen, Tze-Chiang ; Warnock, James D.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
10/1/1989 12:00:00 AM
Abstract :
An emitter-coupled logic (ECL) gate with an AC-coupled active pull-down emitter-follower stage that gives high speed at lower power is described. Significant reduction of the speed-power product can be achieved over the conventional ECL gate. The speed/power advantages of the circuit have been demonstrated in a double-poly, trench-isolated, self-aligned bipolar process with 0.8- mu m (mask) emitter width. Unloaded gate delays of 21 ps at 4.1 mW/gate, 23 ps at 2.1 mW/gate, and 35 ps at 1.1 mW/gate have been measured.
Keywords :
bipolar integrated circuits; emitter-coupled logic; integrated logic circuits; logic gates; 0.8 micron; 1.1 to 4.1 mW; 21 to 35 ps; AC-coupled active pull-down stage; ECL gate; double-poly; emitter-coupled logic; emitter-follower stage; high speed; power-reduction; self-aligned bipolar process; trench-isolated; unloaded gate delays; Capacitance; Circuits; Delay; Inverters; Logic gates; Power dissipation; Propagation delay; Resistors; Silicon; Switches; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1989.572601
