A 4-bit Josephson data processor chip

The authors describe design and experimental results of a Josephson data processor, designed to demonstrate the possibility of a Josephson computer system with a gigahertz clock. It is a stored-program-type full processor including both a data path and a control path, and is constructed from 2066 three-junction interferometer devices on a 5*5-mm² die. An eight-instruction set to enable the basic operations of digital signal processing is implemented. The design rule is 2.5 mu m. The junctions were fabricated using an Nb-AlO_x-Nb process. A new latchup-free DC flip-flop is used in the registers. A DC output buffer eliminates crosstalk from the AC power to the output signals. A stacked AC supply reduces the required AC current amplitude by one quarter. The power dissipation is 25 mW and minimum gate delay is 9 ps. Operation could be confirmed up to a 1.02-GHz clock frequency.