A pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor

Author

Benschneider, Bradley J. ; Bowhill, William J. ; Copper, E.M. ; Gavrielov, Moshe N. ; Gronowski, Paul E. ; Maheshwari, Vijay K. ; Peng, Victor ; Pickholtz, Jeffrey D. ; Samudrala, Sridhar

Author_Institution

Digital Equipment Corp., Hudson, MA, USA

Volume

24

Issue

5

fYear

1989

fDate

10/1/1989 12:00:00 AM

Firstpage

1317

Lastpage

1323

Abstract

A 135K transistor, uniformly pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor chip is described. The execution unit is capable of sustaining pipelined performance of one 32-bit or 64-bit result every 20 ns for all operations except double-precision multiply (40 ns) and divide. The chip employs an exponent difference prediction scheme and a unified leading-one and sticky-bit computation logic for the addition and subtraction operations. A hardware multiplier using a radix-8 modified Booth algorithm and a divider using a radix-2 SRT algorithm are employed.

Keywords

CMOS integrated circuits; digital arithmetic; microprocessor chips; pipeline processing; 20 ns; 40 ns; 50 MHz; 64 bit; CMOS; addition; divider; execution unit; exponent difference prediction scheme; floating-point arithmetic processor; hardware multiplier; microprocessor; processor chip; radix-2 SRT algorithm; radix-8 modified Booth algorithm; sticky-bit computation logic; subtraction; unified leading-one; uniformly pipelined; CMOS logic circuits; CMOS process; CMOS technology; Floating-point arithmetic; Hardware; Helium; Logic; Logic arrays; Pipelines; Process control; Semiconductor device measurement;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1989.572606

Filename

572606