A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit

Author

Kaneko, Katsuyuki ; Okamoto, Tadashi ; Nakajima, Masaitsu ; Nakakura, Yasuhiro ; Gokita, Satoshi ; Nishikawa, Junji ; Tanikawa, Yuji ; Kadota, Hiroshi

Author_Institution

Semicond. Research Center, Matsushita Electr. Ind. Co., Ltd., Osaka, Japan

Volume

24

Issue

5

fYear

1989

fDate

10/1/1989 12:00:00 AM

Firstpage

1331

Lastpage

1340

Abstract

A microprocessor designed as a processing element of a scientific parallel computer system is described. This chip consists of a simple integer processor core and dedicated floating-point hardware and executes 64-bit floating-point addition, subtraction, and multiplication at a rate of every 50 ns and division every 350 ns. The processor, which employs RISC architecture and Harvard-style bus organization, executes most of the 47 instructions in one 50-ns cycle. The chip is fabricated in 1.2- mu m n-well CMOS technology, containing 440K transistors in a 14.4*13.5-mm² die. The authors provide an overview of the processor, especially focusing on the functions for a parallel system, floating-point hardware, and the new divide algorithm.

Keywords

CMOS integrated circuits; VLSI; digital arithmetic; microprocessor chips; parallel processing; reduced instruction set computing; 1.2 micron; 20 MFLOPS; 350 ns; 50 ns; 64 bit; Harvard-style bus organization; RISC architecture; VLSI; addition; dedicated floating-point hardware; division; floating-point unit; integer processor core; microprocessor; multiplication; n-well CMOS technology; scientific parallel computer system; subtraction; CMOS technology; Computer architecture; Concurrent computing; Distributed computing; Hardware; High performance computing; Microprocessors; Process design; Reduced instruction set computing; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1989.572610

Filename

572610