DocumentCode :
1467493
Title :
An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAM
Author :
Yamaguchi, Kunihiko ; Nanbu, Hiroaki ; Kanetani, Kazuo ; Homma, Noriyuki ; Nakamura, Tohru ; Ohhata, Kenichi ; Uchida, Akihisa ; Ogiue, Katsumi
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Volume :
24
Issue :
5
fYear :
1989
fDate :
10/1/1989 12:00:00 AM
Firstpage :
1390
Lastpage :
1396
Abstract :
An experimental soft-error-immune 64-kbit 3-ns ECL RAM has been developed. This high performance is achieved by using a soft-error-immune switched-load-resistor memory cell with clamp transistors, an upward-transistor decoder utilizing a SIdewall-base COntact Structure (SICOS) upward transistor for the AND gate, a Darlington word driver with advanced discharge circuits, and 0.8- mu m SICOS technology. High-load and low-load resistors in this new memory cell are formed by using double-layer polysilicon for the base and emitter electrodes in the SICOS structure. This results in a small cell size (498 mu m2) and a reasonable chip size (85.8 mm2). An accelerated soft-error test using americium alpha source shows that the new 64-kbit RAM has sufficient soft-error immunity, in spite of its small cell capacitance which is about one third that of conventional RAM´s. In addition to the new memory cell, the upward-transistor decoder and the Darlington word driver with advanced discharge circuits make it possible to realize a high-speed, large-capacity bipolar RAM, while maintaining soft-error immunity.
Keywords :
VLSI; bipolar integrated circuits; emitter-coupled logic; integrated circuit technology; integrated memory circuits; random-access storage; 0.8 micron; 3 ns; 64 kbit; AND gate; Darlington word driver; ECL; SICOS technology; accelerated soft-error test; alpha particle immunity; bipolar RAM; chip size; clamp transistors; discharge circuits; double-layer polysilicon; experimental RAM; high speed RAM; small cell capacitance; small cell size; soft-error-immune; switched-load-resistor memory cell; upward-transistor decoder; Clamps; Decoding; Driver circuits; Electrodes; Life estimation; Random access memory; Read-write memory; Resistors; Switching circuits; Transistors;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1989.572620
Filename :
572620
Link To Document :
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