A 10-ps resolution, process-insensitive timing generator IC

Describes a novel circuit configuration and design technique for a high-speed timing generator IC with a 10-ps delay-time resolution. This circuit is composed of multistage delay units in matrix form. In each unit, delay time is finely controlled by loading transistor junction capacitance on an LCML inverter gate and is roughly done by the serial stage numbers of the gate. A dedicated delay-unit IC has been built by an Si bipolar process called SST-1A. The circuit demonstrates a high delay-time resolution of 10 ps at a clock rate of up to 1 GHz. Furthermore, an innovative process-insensitive design technique based on a polynomial formulation for the delay time is proposed. This will be effective in realizing a long delay circuit with high delay resolution.