Title :
Behavior analysis of CMOS D flip-flops
Author :
Chao, Jonathan, II ; Johnston, Cesar A.
Author_Institution :
Bellcore, Morristown, NJ, USA
fDate :
10/1/1989 12:00:00 AM
Abstract :
The authors analyze two D flip-flops (DFF´s) generally considered to be the fastest (and most widely used), and compare their speed performance and their robustness against clock skew when a two-phase clocking scheme is applied. The effect of clock skew on their speed and proper logic operation is analyzed and verified with spice simulation.
Keywords :
CMOS integrated circuits; flip-flops; integrated logic circuits; CMOS D flip-flops; behaviour analysis; clock skew effects; dynamic D flip flops; logic operation; robustness against clock skew; speed performance; spice simulation; two-phase clocking scheme; Analytical models; CMOS logic circuits; Clocks; Delay; Flip-flops; Latches; Master-slave; Performance analysis; Robustness; SPICE; Silicon;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1989.572637
