IDDQ testing: issues present and future

I_DDQ testing has emerged from a company specific CMOS IC test technology in the 1960s and 1970s to become a worldwide accepted technique that is a requirement for low defective parts per million levels and failure rates. It is the single most sensitive test method to detect CMOS IC defects, and an abundance of studies have laid a solid foundation for why this is so. The I_DDQ test uses the quiescent power supply current of logic states as an indication of defect presence. Its major requirement for maximum efficiency is that the design implement nanowatt power levels (nanoampere supply current) in the quiescent portion of the power supply current. No direct connections are allowed between V_DD and V_SS during the quiescent period. I_DDQ testing has increased significantly since 1990, highlighting problems and driving solutions not addressed by the high reliability manufacturers of earlier technologies. Faster I_DDQ instrumentation and better software tools to generate and grade I_DDQ test patterns result from this increased interest. We address two major issues confronting I_DDQ testing: yield loss and increased background current of deep submicron IC technologies projected by the Semiconductor Industry Association/Sematech road map. Both issues are points of controversy