Physics-Based Models for EM and SM Simulation in Three-Dimensional IC Structures

Relaxation of stress generated inside through-silicon via (TSV), in regions of interconnect and regions of silicon adjusted to TSV by microstructure evolution during high-temperature anneal and by wafer/die cooling down to test/operation conditions, is critical for establishing a final equilibrium state. A model for stress relaxation governed by vacancy generation and migration is developed. The comparative study of the steady-state distributions of stress and concentrations of vacancies and plated atoms in via-last and via-middle TSVs allows us to conclude that different types of TSVs are characterized by miniscule differences in the level of generated stress. It is found that the grain size distribution along the TSV height can affect the level of generated stress. TSVs with the largest grains, located in the TSV center, and the smaller ones, located in the TSV top and bottom, seem to generate a smaller outside stress compared to other simulated grain size distributions. It is shown that additional stress gradients in interconnect segments, generated by nearby TSVs, can be relaxed at the proper planed anneal step. The performed simulation analysis allows us to conclude that the introduction of TSVs as a new element in 3-D IC stacking technology does not introduce any significant changes in the EM-related reliability.