Title :
How ATE planning affects LSI manufacturing cost
Author :
Nakamae, Kojl ; Sakamoto, Homare ; Fujioka, Hlromu
Author_Institution :
Fac. of Eng., Osaka Univ., Japan
Abstract :
To analyze the effects of automatic test equipment planning on total LSI manufacturing cost cost per chip, we simulate manufacturing cost by combining discrete event simulation and detailed parametric models of the LSI manufacturing system. This combination provides a more realistic evaluation than previous methods. For our example of ATE planning, we optimize the distribution of LSI testers between the wafer test process and final test process for cost per chip
Keywords :
automatic test equipment; discrete event simulation; integrated circuit manufacture; integrated circuit testing; large scale integration; ATE planning; LSI manufacturing cost; LSI manufacturing system; LSI testers; automatic test equipment planning; discrete event simulation; final test process; manufacturing cost simulation; parametric models; realistic evaluation; total LSI manufacturing cost cost per chip; wafer test process; Analytical models; Automatic test equipment; Costs; Discrete event simulation; Large scale integration; Manufacturing automation; Manufacturing systems; Parametric statistics; Testing; Virtual manufacturing;
Journal_Title :
Design & Test of Computers, IEEE
