Low power architecture for motion compensation filter in a 4K Ultra HD video codec accelerator

Video codec accelerators in hand-held devices are driving the need for low power operation. Motion Compensation in a video codec performs interpolation on blocks of reference image if the motion-vectors refer to fractional pixel positions to form the prediction image for inter macro-blocks. In this paper, we present low power architecture for this motion compensation filter engine used in a 4K Ultra HD AVC accelerator. The paper presents an on-the-fly pixel padding approach without which the DDR bandwidth and power for the output frame in a decoder would have become worse by 9.4% for a full-HD operation. The paper also describes selective transpose - a novel approach to reduce filter engine computation and power. The whole filter engine dissipates less than 5 mW for 4K UHD decoder in a 28nm low power process.