Title :
Undetectable transition faults under broadside tests with constant primary input vectors
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fDate :
3/1/2012 12:00:00 AM
Abstract :
In a broadside test, a scan-in operation is followed by two functional clock cycles where primary input vectors, denoted by v0 and v1, are applied. Because of tester limitations that prevent the primary input vectors from being changed at speed, broadside tests are computed under the constraint where v0=v1. This results in a loss of delay fault coverage. This study develops a fast procedure for identifying transition faults that are undetectable by broadside tests under the constraint v0=v1. Faults that are undetectable because of this constraint are undetectable because of tester limitations and not because of the logic in the circuit. These faults may be able to affect the circuit during functional operation, when the primary input vectors are unconstrained. In this case the faults are important to detect. A fast procedure for identifying undetectable transition faults under the constraint v0=v1 provides a quantitative measure of the effect of this constraint on the achievable fault coverage without performing test generation. If it turns out that the effect on fault coverage is unacceptable, other solutions may be used without first performing test generation.
Keywords :
automatic test pattern generation; fault diagnosis; logic testing; vectors; broadside tests; constant primary input vectors; delay fault coverage; functional clock cycles; quantitative measure; scan-in operation; test generation; tester limitations; transition fault identification; undetectable faults; undetectable transition faults;
Journal_Title :
Computers & Digital Techniques, IET
DOI :
10.1049/iet-cdt.2011.0097