Title :
Instruction Set Innovations for the Convey HC-1 Computer
Author_Institution :
Convey Comput. Corp., Richardson, TX, USA
Abstract :
The Convey HC-1 is a heterogeneous computing system based on an industry-standard Intel processor and a proprietary coprocessor that share virtual memory and an instruction stream, creating a hybrid-core computing system. The coprocessor architecture supports user-defined, dynamically loadable instruction sets. Managing the decoding, dispatch, and execution of completely user-defined instructions requires an innovative approach to system design and operation.
Keywords :
coprocessors; instruction sets; parallel architectures; Convey HC-1 computer; coprocessor architecture; dynamically loadable instruction sets; heterogeneous computing system; hybrid-core computing system; industry-standard Intel processor; instruction set innovations; instruction stream; user-defined instructions; virtual memory; Acceleration; Application software; Computer aided instruction; Computer architecture; Coprocessors; Field programmable gate arrays; Logic programming; Parallel processing; Programmable logic arrays; Technological innovation; FPGAs; accelerators; coprocessors; heterogeneous computing; hybrid-core computing; instruction set design; reconfigurable computing;
Journal_Title :
Micro, IEEE
