Design and verification of five port router for network on chip

Traditional system on chip (SOC) designs offer integrated solutions to exigent design tribulations in areas which necessitate outsized computation and restriction in certain area. Because of the common bus architecture in SOC system, performance becomes sluggish which limits the processing speed. The network on chip (NOC), due to their characteristics such as scalability, flexibility, high bandwidth have been proposed as a valid approach to meet communication requirements in SoC, where common bus architecture replaced by network. The communication on network on chip is carried out by means of router, so for implementing better NOC, the router should be efficiently design. In this paper we present the design and verification of router for Mesh topology using Verilog HDL which supports five parallel connections at the same time. It uses store and forward type of flow control and FSM controller deterministic routing which improves the performance of router. Design unit is targeted to Sparten 3E xc3s500e-4fg320 FPGA device and simulated in XILINX 13.1 Software.