Multiplexer-based array multipliers

Author

Pekmestzi, Kiamal Z.

Author_Institution

Dept. of Electr. Eng., Nat. Tech. Univ. of Athens, Greece

Volume

48

Issue

1

fYear

1999

fDate

1/1/1999 12:00:00 AM

Firstpage

15

Lastpage

23

Abstract

A new algorithm for the multiplication of two n-bit numbers based on the synchronous computation of the partial sums of the two operands is presented. The proposed algorithm permits an efficient realization of the parallel multiplication using iterative arrays. At the same time, it permits high-speed operation. Multiplier arrays for positive numbers and numbers in two´s complement form based on the proposed technique are implemented. Also, an efficient pipeline form of the proposed multiplication scheme is introduced. All multipliers obtained have low circuit complexity permitting high-speed operation and the interconnections of the cells are regular, well-suited for VLSI realization

Keywords

VLSI; circuit complexity; digital arithmetic; interconnections; parallel processing; VLSI realization; circuit complexity; high-speed operation; multiplexer-based array multipliers; n-bit numbers; parallel multiplication; partial sums; pipeline form; synchronous computation; Complexity theory; Delay; Integrated circuit interconnections; Iterative algorithms; Pipelines; Very large scale integration;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.743408

Filename

743408