DocumentCode
1468633
Title
A high-speed reduced-size adder under left-to-right input arrival
Author
Takagi, Naofumi ; Horiyama, Takashi
Author_Institution
Dept. of Inf. Eng., Nagoya Univ., Japan
Volume
48
Issue
1
fYear
1999
fDate
1/1/1999 12:00:00 AM
Firstpage
76
Lastpage
80
Abstract
An efficient parallel adder under left-to-right input arrival is proposed. Making full use of the delay of the input arrival, it produces the sum within a small constant delay after the arrival of the final bits. Its amount of hardware is proportional to the operand length. It can be applied to the quotient conversion in an array divider
Keywords
adders; logic gates; array divider; high-speed reduced-size adder; left-to-right input arrival; parallel adder; quotient conversion; small constant delay; Added delay; Adders; Combinational circuits; Delay effects; Digital systems; Hardware; Logic gates; Size measurement;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.743413
Filename
743413
Link To Document