Self-tested self-synchronization circuit for mesochronous clocking

Author

Mu, Fenghao ; Svensson, Christer

Author_Institution

SwitchCore, Lund, Sweden

Volume

48

Issue

2

fYear

2001

fDate

2/1/2001 12:00:00 AM

Firstpage

129

Lastpage

140

Abstract

In large-scale and high-speed systems, global synchronization has been commonly used to protect clocked I/O from data read failure caused by metastability. There are many drawbacks with global synchronization, which will approach its physical limit in the future as system clock frequency and system scale increase simultaneously. Mesochronous clocking overcomes these drawbacks, but without a proper delay or phase control, a metastability problem occurs. Self-tested self-synchronization (STSS) was proposed to solve this problem. In this paper, we describe two STSS methods, STSS-1 and STSS-2, implemented by two-phase input ports for parallel/serial data transfer. Measurements on a test chip for the two methods show that a data rate of 750 Mb/s is reached with 3.6-V power supply in 0.6-μm CMOS. Comparison is made between STSS-1 and STSS-3

Keywords

CMOS digital integrated circuits; VLSI; circuit stability; clocks; integrated circuit interconnections; synchronisation; timing; 0.6 micron; 3.6 V; 750 Mbit/s; CMOS; STSS-1; STSS-2; clocked I/O; data rate; data read failure; mesochronous clocking; metastability; metastability problem; parallel/serial data transfer; self-tested self-synchronization circuit; system clock frequency; system scale; two-phase input ports; Built-in self-test; Circuits; Clocks; Delay; Frequency synchronization; Large-scale systems; Metastasis; Phase control; Power measurement; Protection;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.917781

Filename

917781