• DocumentCode
    1468728
  • Title

    Comments on "Comments on "A systematic approach for design of digit serial signal processing architectures

  • Author

    Bashagha, Akil E.

  • Author_Institution
    Dept. of Eng. & Technol., De Monfort Univ., Leicester, UK
  • Volume
    48
  • Issue
    2
  • fYear
    2001
  • Firstpage
    177
  • Lastpage
    179
  • Abstract
    In the above paper, [see ibid., vol. 47, p. 369-70, 2000] the authors have modified the nonrestoring square root algorithm (Q=/spl radic/A) and its architecture [see ibid., vol. 38, p.358-75, 1991] to give correct results. They claimed that the partial remainder (PR) should be kept as is rather than eliminating its MSB at each step of the algorithm. Since two bits of A are appended to PR at each step of the algorithm, length of kth PR will be 2k rather than k+1 as in the algorithm of [1]. They also suggested that k of 0´s to be appended to the left of the MSB of the radicand to keep its length as that of PR. As a result, k-1 CAS cells are added to the kth row of the architecture. In this comment, it will be shown that most of the additional CAS cells are redundant where only one added CAS cell per each row is enough to compute the correct square root.
  • Keywords
    computer architecture; digital arithmetic; CAS cells; MSB; digit serial signal processing architectures; nonrestoring square root algorithm; partial remainder; radicand; Algorithm design and analysis; Circuits; Computer architecture; Content addressable storage; Digital signal processing; Signal design; Signal processing; Signal processing algorithms;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1057-7130
  • Type

    jour

  • DOI
    10.1109/82.917786
  • Filename
    917786