DocumentCode
1468922
Title
Design of Tunneling Field-Effect Transistors Based on Staggered Heterojunctions for Ultralow-Power Applications
Author
Wang, Lingquan ; Yu, Edward ; Taur, Yuan ; Asbeck, Peter
Author_Institution
GlobalFoundries Inc., Sunnyvale, CA, USA
Volume
31
Issue
5
fYear
2010
fDate
5/1/2010 12:00:00 AM
Firstpage
431
Lastpage
433
Abstract
This letter presents the design of a tunneling FET with III-V-based tunnel heterojunctions for operation in digital circuits with supply voltages as low as 0.3 V. A representative implementation is predicted to achieve an on-state current drive of 0.4 mA/??m with an off-state current of 50 nA/??m. Comparison with homojunction counterparts reveals that the hetero-tunnel-junction implementations may address better the design tradeoff between on-state drive and off-state leakage.
Keywords
III-V semiconductors; field effect transistors; low-power electronics; tunnel transistors; III-V-based tunnel heterojunctions; digital circuits; staggered heterojunctions; tunneling FET; tunneling field effect transistors; ultralow-power applications; Staggered heterojunction; tunneling FET;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2010.2044012
Filename
5446367
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