Title :
Single-Event Soft Errors in CMOS Logic
Author :
Sayil, Selahattin ; Juyu Wang
Abstract :
In this article, various mechanisms for combinational logic-related radiation induced soft errors such as SE-induced soft delays, SE clock jitter and clock pulse, and SE crosstalk effects have been discussed. Our analysis shows that increasing SE crosstalk noise and delay effects occur with smaller technologies. This work has finally discussed hardening techniques for SE crosstalk noise and delay. Results are shown using HSpice Simulations with interconnect and device parameters derived from Predictive Technology Model for 65 nm.
Keywords :
CMOS logic circuits; combinational circuits; crosstalk; radiation hardening (electronics); CMOS logic; HSpice simulations; SE clock jitter; SE crosstalk effects; SE-induced soft delays; clock pulse; combinational logic; device parameters; hardening techniques; predictive technology model; radiation induced soft errors; single-event soft errors; size 65 nm; CMOS integrated circuits; Crosstalk; Integrated circuit reliability; Logic gates; Noise measurement; Signal processing; Transient analysis;
Journal_Title :
Potentials, IEEE
DOI :
10.1109/MPOT.2011.2178191