Title :
Design and implementation of two stage 5-bit pipelined SAR ADC
Author :
Ananda, Padmanaban M. ; Ponnambalam, Maran ; Chandramani, Premanand V.
Author_Institution :
SSN Coll. of Eng., Chennai, India
Abstract :
A 250 MS/s cascaded two-stage 5-bit pipelined SAR ADC in 90nm CMOS was designed and validated. Elimination of passive components leads to an improvement in power utilization, improvement in speed and at the same time is not limited by process variations. The SAR ADC design was validated as a Matlab/Simulink macro model and verified in 90nm CMOS through Agilent ADS. Successive approximation for each stage is achieved through a binary search in a round robin mode that reduces the approximation time. DNL was observed to be 0.7 LSB.
Keywords :
CMOS integrated circuits; analogue-digital conversion; integrated circuit design; CMOS; cascaded SAR ADC; passive component elimination; pipelined SAR ADC; power utilization; size 90 nm; CMOS integrated circuits; Clocks; Delays; Inverters; Software packages; Switching circuits; Analog-to-digital converter (ADC); CMOS; Pipelined SAR ADC; successive approximation (SAR);
Conference_Titel :
Communications and Signal Processing (ICCSP), 2014 International Conference on
Conference_Location :
Melmaruvathur
Print_ISBN :
978-1-4799-3357-0
DOI :
10.1109/ICCSP.2014.6949991
