DocumentCode :
1470334
Title :
Efficient H.264/AVC software CAVLC decoder based on level length extraction
Author :
Uchihara, Naofumi ; Hayakawa, Hiroki ; Kasai, Hiroyuki
Author_Institution :
Grad. Sch. of Inf. Syst., Univ. of Electro-Commun., Tokyo, Japan
Volume :
58
Issue :
1
fYear :
2012
fDate :
2/1/2012 12:00:00 AM
Firstpage :
146
Lastpage :
153
Abstract :
This paper presents a proposal for an efficient software CAVLC decoder architecture in H.264/AVC based on level length extraction (LLE). Especially, level-decoding in a CAVLC decoder is addressed. Its features are summarized in two parts: higher efficient pipeline processing of level decoding, and simultaneous multiple calculations of multiple level codes separated from level decoding loop using Single Instruction Multiple data (SIMD) instruction. The former is achieved by separating Level calculation from Level parsing based on the LLE scheme, and removing branch operations in the level decoding loop. These improve the pipelineprocessing efficiency. The latter removes Level calculation from the level decoding loop, and uses multiple Level calculations based on SIMD instruction. The proposed schemes emphasize the software architecture. They are therefore applicable to general computers. Consequently, they can also be integrated with other CAVLC opimization schemes for CoeffToken, TotalZeros, and RunBefore syntax elements. Based on results of evaluation experiments, we confirmed that the improved pipeline processing achieved 22% faster decoding speed compared with the conventional method, which used only the LLE scheme. The SIMD-based Level calculation also achieved a 38% faster decoder than before by integrating with the former part.
Keywords :
adaptive codes; audio coding; optimisation; parallel processing; program compilers; software architecture; variable length codes; video coding; CAVLC optimization scheme; CoeffToken syntax element; H.264-AVC software CAVLC decoder architecture; LLE scheme; RunBefore syntax element; SIMD instruction; SIMD-based level calculation; TotalZeros syntax element; branch operation; decoding speed; general computer; higher efficient pipeline processing; level decoding loop; level length extraction; level parsing; multiple level calculation; multiple level code; single instruction multiple data instruction; software architecture; Computer architecture; Decoding; Encoding; Mathematical model; Pipeline processing; Registers; Software;
fLanguage :
English
Journal_Title :
Consumer Electronics, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-3063
Type :
jour
DOI :
10.1109/TCE.2012.6170067
Filename :
6170067
Link To Document :
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