DocumentCode
1470414
Title
A fast algorithm for minimizing the Elmore delay to identified critical sinks
Author
Borah, Manjit ; Owens, Robert M. ; Irwin, Mary Jane
Author_Institution
Cadence Design Syst. Inc., San Jose, CA, USA
Volume
16
Issue
7
fYear
1997
fDate
7/1/1997 12:00:00 AM
Firstpage
753
Lastpage
759
Abstract
A routing algorithm that generates a Steiner route for a set of sinks with near optimal Elmore delay to the critical sink is presented. The algorithm outperforms the best existing alternative for Elmore-delay-based critical sink routing. With no critical sinks present, the algorithm produces routes comparable to the best previously existing Steiner router. Since performance-oriented layout generators employ iterative techniques that require a large number of calls to the routing algorithm for layout evaluation, a fast algorithm for routing is desirable. The algorithm presented here has a fast (O(n2), where n is the number of points) and practical implementation using simple data structures and techniques
Keywords
circuit layout; circuit optimisation; delays; iterative methods; minimisation; network routing; Elmore delay minimization; Steiner route; critical sink; iterative technique; performance-oriented layout generator; routing algorithm; Capacitance; Data structures; Delay lines; Feedback; Integrated circuit interconnections; Iterative algorithms; Joining processes; Performance evaluation; Routing; Wire;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.644036
Filename
644036
Link To Document