Digital model for switching transistors in series-gated ECL

A digital model is proposed that allows function verification and timing analysis of series-gated ECL to be performed on a logic simulation. Traditionally, an analogue simulator will be necessary because series-gated ECL circuits are constructed from transistors rather than primitive gates. The model is meant to replace each switching transistor in a series-gated ECL. A simulation time at least two magnitudes lower has bean achieved.