Title :
Design of a novel architecture of 3-D discrete wavelet transform for image processing through video compression
Author :
Challa, Komala Vani ; Krishna, P. Vamsi ; Rao, Chintapanti Nageswar
Author_Institution :
Dept. of Electron. & Commun. Eng., V.V. Coll. of Eng., Tisaiyenvillai, India
Abstract :
This paper presents a low power and high speed 3-D-DWT (three-dimensional discrete wavelet transform) architecture for image compression. With the recent expansion of multimedia applications and the need for delivering compressed bit streams over heterogeneous networks, scalability has become an important feature for video coders. The 3-D discrete wavelet transform provides a natural spatial resolution and frame rate scalability. Scalability is achieved in temporal and spatial resolutions, as well as in quality. The advantages of this scheme when they are compared with those of existing ones are in terms of complexity, low power, high throughput, low latency and minimum storage requirement. The proposed architecture has been successfully implemented on Xilinx Spartan 3E series field-programmable gate array, suitable for real-time compression.
Keywords :
data compression; discrete wavelet transforms; field programmable gate arrays; logic design; video codecs; video coding; 3D discrete wavelet transform; Xilinx Spartan 3E series; field programmable gate array; high speed 3D-DWT; image compression; image processing; low power 3D-DWT; multimedia applications; real time compression; video coder; video compression; Computer architecture; Discrete wavelet transforms; Frequency modulation; Image coding; Matrix decomposition; Spatial resolution; Discrete Wavelet Transform (DWT); Image Compression; VLSI Architecture; Video Coder;
Conference_Titel :
Communications and Signal Processing (ICCSP), 2014 International Conference on
Conference_Location :
Melmaruvathur
Print_ISBN :
978-1-4799-3357-0
DOI :
10.1109/ICCSP.2014.6950016