A new fast DCT algorithm and its systolic VLSI implementation

Author

Chang, Yu-Tai ; Wang, Chin-Liang

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

Volume

44

Issue

11

fYear

1997

fDate

11/1/1997 12:00:00 AM

Firstpage

959

Lastpage

962

Abstract

The authors present a new fast algorithm along with its systolic array implementation for computing the N-point discrete cosine transform (DCT), where N is a power of two. The architecture requires log₂N multipliers and can evaluate one complete N-point DCT (i.e., N transform samples) every N clock cycles. Due to the features of regularity and modularity, it is well suited to VLSI implementation. As compared to existing systolic DCT designs with the same throughput performance, the proposed one involves much less hardware complexity

Keywords

VLSI; algorithm theory; digital arithmetic; digital signal processing chips; discrete cosine transforms; mathematics computing; matrix multiplication; signal processing; systolic arrays; discrete cosine transform; fast DCT algorithm; hardware complexity reduction; systolic VLSI implementation; Clocks; Computer architecture; Digital signal processing; Discrete cosine transforms; Hardware; Process design; Signal processing algorithms; Systolic arrays; Throughput; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.644050

Filename

644050