Steiner tree optimization for buffers, blockages, and bays

Author

Alpert, Charles J. ; Gandham, Gopal ; Hu, Jiang ; Neves, Jose L. ; Quay, Stephen T. ; Sapatnekar, Sachin S.

Author_Institution

Res. Lab., IBM Corp., Austin, TX, USA

Volume

20

Issue

4

fYear

2001

fDate

4/1/2001 12:00:00 AM

Firstpage

556

Lastpage

562

Abstract

Timing optimization is a critical component of deep submicrometer design and buffer insertion is an essential technique for achieving timing closure. This work studies buffer insertion under the constraint that the buffers either: (1) avoid blockages or (2) are contained within preassigned buffer bay regions. We propose a general Steiner-tree formulation to drive this application and present a maze-routing-based heuristic that either avoids blockages or finds buffer bays. We show that the combination of our Steiner-tree optimization with leading-edge buffer-insertion techniques leads to effective solutions on industry designs

Keywords

VLSI; circuit layout CAD; circuit optimisation; integrated circuit design; integrated circuit interconnections; integrated circuit layout; network routing; timing; trees (mathematics); Steiner tree optimization; bays; blockages; buffers; deep submicrometer design; industry designs; leading-edge buffer-insertion techniques; maze-routing-based heuristic; preassigned buffer bay regions; timing closure; timing optimization; Closed-form solution; Delay; Design methodology; Design optimization; Dynamic programming; Heuristic algorithms; Logic; Routing; Timing; Very large scale integration;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.918213

Filename

918213