Bipolar transistor selected P-channel flash memory cell technology

Author

Ohnakado, Takahiro ; Ajika, Natsuo ; Satoh, Shin-ichi

Author_Institution

Advanced Technol. Res. & Dev. Centre, Mitsubishi Electr. Corp., Hyogo, Japan

Volume

48

Issue

5

fYear

2001

fDate

5/1/2001 12:00:00 AM

Firstpage

863

Lastpage

867

Abstract

A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed, where a bipolar transistor embedded in the source region of the cell amplifies cell-read-current and acts as a select transistor. With this cell, not only a very low 1.5 V non-word-line-boosting read operation, but also a sector-erase operation are successfully achieved with only a small cell-size increase over the conventional NOR cell. Moreover, this cell technology maintains all the advantages of the P-channel DIvided-bit-line NOR (DINOR) flash memory

Keywords

CMOS memory circuits; bipolar transistor circuits; flash memories; low-power electronics; 1.5 V; CMOS technology; bipolar transistor selected P-channel; cell-read-current amplification; divided-bit-line NOR flash memory; flash memory cell; low voltage memory; non-word-line-boosting read operation; sector-erase operation; select transistor; small cell-size increase; source region embedded bipolar transistor; Bipolar transistors; Costs; Degradation; EPROM; Energy consumption; Flash memory; Flash memory cells; Laser sintering; Leakage current; Threshold voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.918232

Filename

918232