Title :
On a dual-polarity on-chip electrostatic discharge protection structure
Author :
Wang, Albert Z H ; Tsay, Chen-Hui
Author_Institution :
Integrated Electron. Lab., Illinois Inst. of Technol., Chicago, IL, USA
fDate :
5/1/2001 12:00:00 AM
Abstract :
A novel dual-polarity on-chip electrostatic discharge (ESD) protection structure is designed. The new ESD structure protects IC chips against ESD stressing in the two opposite directions. The ESD structure features symmetric deep-snapback current-voltage (I-V) characteristics, low-impedance active overcurrent discharging path, low holding voltage for overvoltage clamping, fast ESD response of ~0.18 ns, low leakage (~pA), adjustable triggering voltage, and good scalability. It passes 14 KV HBM ESD zapping tests and achieves high ESD-performance-to-Si ratio of ~80 V/μm width. The new ESD structure reduces Si areas consumed by ESD protection units and ESD-induced parasitic effects significantly
Keywords :
electrostatic discharge; integrated circuit design; integrated circuit reliability; integrated circuit testing; leakage currents; protection; 0.18 ns; 14 kV; ESD stressing; ESD structure; ESD-induced parasitic effects; ESD-performance-to-Si ratio; HBM ESD zapping tests; IC chip protection; IC reliability; consumed Si area reduction; dual-polarity on-chip electrostatic discharge protection structure; fast ESD response; low holding voltage; low leakage adjustable triggering voltage; low-impedance active overcurrent discharging path; overvoltage clamping; scalability; symmetric deep-snapback current-voltage characteristics; BiCMOS integrated circuits; Circuit simulation; Clamps; Electrostatic discharge; Low voltage; Predictive models; Protection; Scalability; Semiconductor device reliability; Testing;
Journal_Title :
Electron Devices, IEEE Transactions on
