Built-in Self-Calibration Circuit for Monotonic Digitally Controlled Oscillator Design in 65-nm CMOS Technology

This brief presents a built-in self-calibration (BISC) circuit to correct nonmonotonic responses in a digitally controlled oscillator (DCO) with a cascading structure. Generally speaking, a cascading DCO structure has the advantages of low power consumption and a small chip area. Nevertheless, when a subfrequency band is changed, an overlap region between subfrequency bands causes a large phase error and cycle-to-cycle jitter in an output clock. The proposed BISC circuit can reduce this problem; thus, it is very suitable for a low-power all-digital phase-locked loop design in system-on-a-chip applications. The proposed DCO, implemented with a standard performance 65-nm complementary metal-oxide-semiconductor process, can output frequency ranges from 47.8 to 538.7 MHz. The total power consumption of the DCO with a calibration circuit is 0.142 mW at 58.7 MHz and 0.205 mW at 481.6 MHz.