• DocumentCode
    1471709
  • Title

    CMOS compatible HV gate-shifted LDD-NMOS

  • Author

    Santos, P.M. ; Casimiro, A.P. ; Lança, M. ; Simas, M. I Castro

  • Author_Institution
    Inst. de Telecimunicacoes, Tech. Univ. Lisbon, Portugal
  • Volume
    48
  • Issue
    5
  • fYear
    2001
  • fDate
    5/1/2001 12:00:00 AM
  • Firstpage
    1013
  • Lastpage
    1015
  • Abstract
    This brief presents an improvement of lightly doped drain (LDD) FET based on a drain engineering technique-the gate-shifting. Gate-shifted LDD (GSLDD) devices were fabricated in a submicron CMOS technology with no extra processing steps. Breakdown voltages in the range of 50 V and specific ON-resistances in the range of 2-4 mΩ·cm2 were attained
  • Keywords
    CMOS integrated circuits; impact ionisation; power MOSFET; semiconductor device breakdown; 50 V; CMOS compatible HV gate-shifted LDD-NMOS; breakdown voltages; drain engineering technique; gate-shifted LDD devices; gate-shifting; lightly doped drain FET; specific on-resistance; submicron CMOS technology; CMOS process; CMOS technology; Circuits; Electrodes; FETs; Impact ionization; Low voltage; MOS devices; Silicon; Telecommunications;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.918255
  • Filename
    918255
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1471709