DocumentCode
1471722
Title
The nonvolatile cell hidden in standard CMOS logic technologies
Author
Lovett, Simon J.
Author_Institution
Cypress Semicond., San Jose, CA, USA
Volume
48
Issue
5
fYear
2001
fDate
5/1/2001 12:00:00 AM
Firstpage
1017
Lastpage
1018
Abstract
An electrically programmable cell is described which is latently available in virtually all modern CMOS logic processes. The cell consists of an n-ch and a p-ch device with their gates coupled together to form the floating gate. The element may be used to adjust circuit function, timing, zero adjust, etc
Keywords
CMOS logic circuits; programmable circuits; timing; 0.25 mum; 3.3 V; CMOS logic technologies; circuit function; coupled gates; electrically programmable cell; floating gate; hidden nonvolatile cell; n-ch device; one time programmable nonvolatile cell; p-ch device; timing; zero adjust; Breakdown voltage; CMOS logic circuits; CMOS process; CMOS technology; Costs; EPROM; Electric breakdown; Logic devices; Substrates; Tunneling;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.918257
Filename
918257
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