DocumentCode
147203
Title
2T 2:1 MUX based 1 bit full adder design
Author
Kumar Singh, Navneet ; Kumari Sharma, Purnima
Author_Institution
Dept. of Electron. & Commun. Eng., North Eastern Regional Inst. of Sci. & Technol., Nirjuli, India
fYear
2014
fDate
3-5 April 2014
Firstpage
1491
Lastpage
1493
Abstract
This paper puts forward a methodology for designing 1 bit full adder using a 2T mux. The 2T mux is combined in a specific manner to get a full adder with sum and carry output. The resulting 1 bit full adder is made up of 16 transistors. The simulation is done using Cadence Virtuoso Simulator using 180nm technology and 1.8V power supply. The results show the efficiency of the design.
Keywords
adders; logic gates; transistor circuits; Cadence Virtuoso simulator; MUX; full adder design; size 180 nm; transistors; voltage 1.8 V; word length 1 bit; Adders; CMOS integrated circuits; Computers; Microstrip; Robustness; Transistors; carry; full adder; mux; sum; xor;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications and Signal Processing (ICCSP), 2014 International Conference on
Conference_Location
Melmaruvathur
Print_ISBN
978-1-4799-3357-0
Type
conf
DOI
10.1109/ICCSP.2014.6950097
Filename
6950097
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