Testing an ADC linearized with pseudorandom dither

When a pure sinewave is digitized by an analog-to-digital converter (ADC), the errors are determined by the input voltage and, hence, the phase of the sinewave. The errors generate signal harmonics coherently. One technique used to reduce the harmonic distortion is dithering by combining a pseudorandom wide bandwidth dither signal with the input signal. When pseudorandom dither is added to a sinusoidal signal, it randomizes the ADC errors with respect to the sinewave so that the errors cannot add coherently. The dominant effect of the dither component is to reduce large spurious harmonic distortion components by spreading them into many smaller ones. This paper presents a test method for testing an ADC linearized with pseudorandom dither. We present results of testing a 12-bit, 5 MHz converter and a state-of-the-art, 14-15-bit, 10 MHz converter