A high speed area efficient FIR filter using floating point dadda algorithm

Multiplier are the fundamental components in all digital signal processing systems the hot of the Mac unit is floating point multiplier. The largest contribute to power consumption in floating point multiplier is due to generation and reduction of partial product. Our proposed work dealing with Dadda multiplier based FIR filter which consumes low power with high performance. Transposed form of FIR filter is taken to evaluate the efficiency of floating point multiplier using Dadda algorithm.