Hardware accelerators for timing simulation of VLSI digital circuits

Designs are presented of two hardware engines for timing simulation. Both use the forward Euler integration algorithm to solve the differential equations that model the circuit. The simplicity of this algorithm compensates for the small time-step required. By structuring the algorithm to reduce data dependencies and maximize functional parallelism, a pipelined implementation is used. The use of a compact data representation and static integration stability checks results in a simple, yet fast, processor. The first engine provides a uniprocessor implementation that explores the feasibility of this approach to timing simulation. The second engine is an enhancement of the first. It uses a multiprocessor structure with a high-bandwidth interconnection network to support parallel simulation. Circuit inactivity is also used in a selective trace algorithm. The speed of this accelerator is high, allowing the simulation of circuits with over 100000 transistors in under one second per simulated clock cycle