Serial and parallel concatenated code for MC DS CDMA using Verilog HDL

Multi Carrier Direct Sequence Code Division Multiple Access(MC DS CDMA) technique is the future generation mobile communication system and to access technology in future advances. Serial and Parallel concatenated codes are used for correcting the errors in data transmission. We proposed hybrid concatenated code for MC DS CDMA structure and estimate parameters like memory and design time. Use of interleavers are reduce the burst errors between outer and inner code of encoding and decoding operation in the MC DS CDMA model. Modelsim synthesis technology used for simulate the entire model and Verilog Hardware Description Languages (HDL) are used for design the codes of MC DS CDMA systems.