Efficient implementation of AES algorithm on FPGA

AES represents an algorithm for advanced encryption standard consist of different operations required in the steps of encryption and decryption. The proposed architecture is based on optimizing area in terms of reducing no of slices required for design of AES algorithm in VHDL. This paper produces 3 step designs. AES (TOP), AES (1-9ROUNDS), AES(LAST ROUND) in which code is divided in to three parts instead of 4 groups in single round. This paper presents AES-128 bit algorithm design consist of 128 bit symmetric key & Xilinx ISE 14.1 Project Navigator used for synthesis and simulation of this proposed architecture purpose.