Low power and high performance achievement using Constant Delay Logic Style

The high performance energy efficient is one of the most important goal and objective in the design of VLSI circuits. To achieve this, new CMOS logic family constant delay (CD) logic is used. The CD logic has contention, C-Q delay and D-Q delay modes. In CD logic, D-Q delay mode proposes a distinct characteristic where the output is pre-calculated before getting the inputs from the previous stage. This logic provides performance improvement over static and dynamic logic styles in multistage circuit block. In accordance with the logic type, the CD logic style is suitable to implement difficult logic expressions such as addition. The three modes of CD logic is designed, simulated and synthesized. Also full adder is designed, simulated and synthesized in transistor level using static, dynamic and CD logic styles in Tanner EDA. The synthesized results of Full Adder demonstrates that Full Adder using CD logic style has lesser delay which enhances the performance and consumes more power than other two logic styles. Low power is likely to be a key objective in VLSI circuit design. To achieve this, low power techniques -Clock Gating and Supply Voltage Scaling are also used in Full Adder and 4-bit Ripple Carry Adder using CD logic style.