A heuristic standard cell placement algorithm using constrained multistage graph model

A fast heuristic algorithm is presented for the constructive placement of standard cells based on the so-called constrained multistage graph (CMSG) model, which has a linear time complexity in the number of cells. The first step of this algorithm performs the row assignment of each cell by converting the circuit connectivity into the CMSG, where each stage of the CMSG corresponds to a cell-row in the final layout. In the second step, called the line sweep method, the position of each cell within the row is determined one by one so that the local channel density is minimized. Experimental results on benchmark circuits show that the proposed algorithm yields very competitive results in terms of the number of feedthrough cells and channel density, which was verified by the comparison of the proposed algorithm with the simulated annealing (SA) and other iterative methods such as pairwise interchange, or generalized force-directed relaxation. A theoretical time complexity analysis performed show that the complexity of the proposed algorithm is O(n), where n denotes the number of cells. This result is substantiated with experimental results