• DocumentCode
    1474030
  • Title

    Interactive Debug of SoCs with Multiple Clocks

  • Author

    Vermeulen, Bart ; Goossens, Kees

  • Author_Institution
    NXP Semicond., Netherlands
  • Volume
    28
  • Issue
    3
  • fYear
    2011
  • Firstpage
    44
  • Lastpage
    51
  • Abstract
    Systems with elaborate multiple clock distributions are a necessity, and the authors address the postfabrication debug of such multiclock systems. Solutions, based on the authors´ communication-centric debug approach, are presented that achieve a consistent snapshot of the system state and force the erroneous state in the face of nondeterminism.
  • Keywords
    clocks; electronic engineering computing; interactive systems; system-on-chip; communication centric debug approach; interactive SoC debugging; multiple clock distribution; postfabrication debug; Debugging; IP networks; Monitoring; Multicore processing; Synchronization; System-on-a-chip; communication-centric debug; consistent global state dumps; debug abstraction techniques; design and test; embedded SoC; handshake signals; multiple clocks; network on chip; silicon debug; silicon validation; software debug;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2011.42
  • Filename
    5733334
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1474030