Title :
Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric
Author :
Yeo, Yee-Chia ; Lu, Qiang ; Ranade, Pushkar ; Takeuchi, Hideki ; Yang, Kevin J. ; Polishchuk, Igor ; King, Tsu-Jae ; Hu, Chenming ; Song, S.C. ; Luan, H.F. ; Kwong, Dim-Lee
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
5/1/2001 12:00:00 AM
Abstract :
We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si/sub 3/N/sub 4/) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO/sub 2/) are observed.
Keywords :
CMOS integrated circuits; CVD coatings; MOSFET; carrier mobility; dielectric thin films; integrated circuit technology; molybdenum; silicon compounds; titanium; C-V characteristics; CMOSFETs; Mo; Mo gate electrode; NMOSFET; PMOSFET; RTCVD process; Si oxy-nitride interfacial layer; Si/sub 3/N/sub 4/ dielectric layer; SiON-Si/sub 3/N/sub 4/; Ti; Ti gate electrode; carrier mobilities; dual-metal gate CMOS technology; gate dielectric stack; n-MOSFETs; p-MOSFETs; rapid-thermal CVD process; rapid-thermal chemical vapor deposition; ultrathin gate dielectric; CMOS technology; Capacitance-voltage characteristics; Chemical vapor deposition; Dielectrics; Electrodes; FETs; MOSFET circuits; Predictive models; Silicon; Titanium;
Journal_Title :
Electron Device Letters, IEEE
