Title :
Optimizations enabled by a decoupled front-end architecture
Author :
Reinman, Glenn ; Calder, Brad ; Austin, Todd
Author_Institution :
Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
fDate :
4/1/2001 12:00:00 AM
Abstract :
In the pursuit of instruction-level parallelism, significant demands are placed on a processor´s instruction delivery mechanism. Delivering the performance necessary to meet future processor execution targets requires that the performance of the instruction delivery mechanism scale with the execution core. Attaining these targets is a challenging task due to I-cache misses, branch mispredictions, and taken branches in the instruction stream. To counter these challenges, we present a fetch architecture that decouples the branch predictor from the instruction fetch unit. A Fetch Target Queue (FTQ) is inserted between the branch predictor and instruction cache. This allows the branch predictor to run far in advance of the address currently being fetched by the cache. The decoupling enables a number of architecture optimizations, including multilevel branch predictor design, fetch-directed instruction prefetching, and easier pipelining of the instruction cache. For the multilevel predictor, we show that it performs better than a single-level predictor, even when ignoring the effects of cycle-timing issues. We also examine the performance of fetch-directed instruction prefetching using a multilevel branch predictor and show that an average 19 percent speedup is achieved. In addition, we examine pipelining the instruction cache to achieve a faster cycle time for the processor pipeline and show that pipelining provides an average 27 percent speedup over not pipelining the instruction cache for the programs examined
Keywords :
computer architecture; performance evaluation; storage management; I-cache misses; branch mispredictions; branch predictor; decoupled front-end architecture; decoupling; fetch architecture; fetch target queue; fetch-directed instruction prefetching; instruction delivery mechanism; instruction-level parallelism; multilevel branch predictor; multilevel branch predictor design; optimizations; pipelining; processor execution targets; Counting circuits; Decoding; Design optimization; Engines; Filling; Joining processes; Pipeline processing; Prefetching; Registers; Retirement;
Journal_Title :
Computers, IEEE Transactions on