DocumentCode :
1474454
Title :
Skew tolerant digital CDR architecture for LVDS video transceiver applications
Author :
Sarmento, J.A.
Author_Institution :
Synopsys Inc., Maia, Portugal
Volume :
46
Issue :
8
fYear :
2010
Firstpage :
578
Lastpage :
580
Abstract :
A fully digital clock and data recovery (CDR) architecture for multi-link applications is presented. The architecture has independent tolerance to inter-channel skew and timing jitter, and does not rely on data-embedded framing information or a specific equalisation sequence. It is therefore especially suited to low-voltage differential signalling (LVDS) video transceiver applications, and is described in that context. Attained skew tolerance is predicted in theory and successfully compared against silicon prototype measurements.
Keywords :
synchronisation; timing jitter; transceivers; video streaming; data recovery; digital clock; equalisation sequence; inter-channel skew; low-voltage differential signalling video transceiver applications; skew tolerant digital CDR architecture; timing jitter;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el.2010.3473
Filename :
5451017
Link To Document :
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