Title :
Skew tolerant digital CDR architecture for LVDS video transceiver applications
Author_Institution :
Synopsys Inc., Maia, Portugal
Abstract :
A fully digital clock and data recovery (CDR) architecture for multi-link applications is presented. The architecture has independent tolerance to inter-channel skew and timing jitter, and does not rely on data-embedded framing information or a specific equalisation sequence. It is therefore especially suited to low-voltage differential signalling (LVDS) video transceiver applications, and is described in that context. Attained skew tolerance is predicted in theory and successfully compared against silicon prototype measurements.
Keywords :
synchronisation; timing jitter; transceivers; video streaming; data recovery; digital clock; equalisation sequence; inter-channel skew; low-voltage differential signalling video transceiver applications; skew tolerant digital CDR architecture; timing jitter;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2010.3473