Some electronic logic circuits for serial-parallel arithmetic

In one form of rapid binary multiplier the number which is to be multiplied is presented serially to a controlled shift register. The multiplier must be presented in parallel to obtain the binary product. It controls the function of the register so that the product is generated serially from it. A variant of this type of multiplier is described in which the control logic is regarded as a recognizable sub-system. A new design for a divider is also suggested which is comparable with that of the multiplier and which uses some control logic which is common to both systems. The method is further extended to include the design of a square-rooter.