Title :
A Digital Envelope Combiner for Switching Power Amplifier Linearization
Author :
Singhal, Nitesh ; Pamarti, Sudhakar
Author_Institution :
Dept. of Electr. Eng., Univ. of California Los Angeles, Los Angeles, CA, USA
fDate :
4/1/2010 12:00:00 AM
Abstract :
A digital envelope combiner (DEC) technique that employs an open-loop transformer-based combination of a bank of two-level polar switching power amplifiers to generate wide-bandwidth modulated radio frequency signals with simultaneously high efficiency and good linearity is presented. The application of the DEC is illustrated by the design and simulation-based verification of a 2.4-GHz 0.13-¿m complementary metal-oxide-semiconductor power amplifier that achieves EVM < -25 dBc, ACPR < -40 dBc, and an average drain efficiency of 37% while generating a 16.25-MHz-bandwidth 8.9-dB-peak-to-average signal power ratio (PAR) 64-state quadrature amplitude modulation signal.
Keywords :
CMOS analogue integrated circuits; power amplifiers; quadrature amplitude modulation; transformers; bandwidth 16.25 MHz; complementary metal-oxide-semiconductor power amplifier; digital envelope combiner; frequency 2.4 GHz; open-loop transformer; peak-to-average signal power ratio; quadrature amplitude modulation; size 0.13 micron; switching power amplifier linearization; two-level polar switching power amplifier; wide-bandwidth modulated radio frequency signal; Broadband amplifiers; Chirp modulation; Digital modulation; Frequency modulation; High power amplifiers; Power amplifiers; Power generation; Radio frequency; Radiofrequency amplifiers; Signal generators; Class E; peak-to-average signal power ratios (PARx); power amplifier (PA); transformer combiner; zero voltage switching (ZVS);
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2010.2043399