DocumentCode :
1475225
Title :
9 K operation of RSFQ logic cells fabricated by NbN integrated circuit technology
Author :
Terai, Hirotaka ; Wang, Zhen
Author_Institution :
Commun. Res. Lab., Minist. of Posts & Telecommun., Kobe, Japan
Volume :
11
Issue :
1
fYear :
2001
fDate :
3/1/2001 12:00:00 AM
Firstpage :
525
Lastpage :
528
Abstract :
We report on the fabrication and the operation of all-NbN rapid single flux quantum (RSFQ) circuits. The NbN integrated circuit consists of NbN/AlN/NbN tunnel junctions, Mo resistors, sputtered SiO2 insulating layers, and 400-nm-thick NbN ground plane and wiring layer. The circuits were fabricated with the minimum junction size of 2 μm×2 μm and the alignment margin of +/-0.5 μm. We designed RSFQ logic cells under critical current density of 2.5 kA/cm 2, sheet resistance of 2 Ω and sheet inductance of 1.4 pH. We experimentally investigated dc bias margin of the fabricated RSFQ cells at 9 K. We observed relatively large dc bias margin of more than +/-25% for a pulse splitter, a confluence buffer and an RS flip-flop, while the dc bias margin of a T flip-flop was less than +/-5%. We succeeded to demonstrate the operation of 16-bit concurrent flow shift register at 9 K
Keywords :
buffer circuits; flip-flops; niobium compounds; shift registers; superconducting logic circuits; 16 bit; 9 K; DC bias margin; Mo resistor; NbN; NbN integrated circuit; NbN/AlN/NbN tunnel junction; RS flip-flop; RSFQ logic cell; SiO2 sputtered insulating layer; T flip-flop; concurrent flow shift register; confluence buffer; critical current density; fabrication technology; ground plane; pulse splitter; sheet inductance; sheet resistance; superconducting digital circuit; wiring layer; Circuits; Critical current density; Fabrication; Flip-flops; Inductance; Insulation; Logic design; Resistors; Shift registers; Wiring;
fLanguage :
English
Journal_Title :
Applied Superconductivity, IEEE Transactions on
Publisher :
ieee
ISSN :
1051-8223
Type :
jour
DOI :
10.1109/77.919398
Filename :
919398
Link To Document :
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