The design of feedback shift registers and other synchronous counters

This paper is concerned with digital sub-systems comprising bistable flip-flops connected to a common source of clock-pulses. This configuration, of which the feedback shift register is the most important special case, is useful for the generation of periodic binary codes and sequences. It is assumed that the building-blocks for these circuits are integrated J-K flip-flops and NAND gates, and design techniques appropriate for this situation are described.