Title :
Pipelined DC-powered SFQ RAM
Author :
Kirichenko, Alex F. ; Sarwana, Saad ; Brock, Darren K. ; Radpavar, Masoud
Author_Institution :
HYPRES Inc., Elmsford, NY, USA
fDate :
3/1/2001 12:00:00 AM
Abstract :
We present the design and test results of components for a superconductor Cryogenic Random Access Memory (CRAM). The 16-Kb RAM design consists of four 4-Kb sub-arrays (blocks) with a 400 ps access time (latency) and a 100 ps cycle time (throughput). Each 4-Kb RAM block comprises a row-accessed 32×128 memory cell array, bipolar line drivers, row decoders, and column sense circuits. The implementation of specially designed distributed Josephson junctions in the sensing circuits reduces the overall size of the blocks and allows the use of smaller dc control currents
Keywords :
pipeline processing; random-access storage; superconducting arrays; superconducting memory circuits; 16 Kbit; Josephson junction; bipolar line driver; column sense circuit; memory cell array; pipelined DC-powered SFQ RAM; row decoder; superconductor cryogenic random access memory; Cryogenics; Decoding; Delay; Driver circuits; Josephson junctions; Random access memory; Read-write memory; Size control; Testing; Throughput;
Journal_Title :
Applied Superconductivity, IEEE Transactions on
